AT89C51CC03C-S3SIM【PDF 11/198 页】IC 8051 MCU FLASH 64K 52PLCC

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108

AT89C51CC03

4182O–CAN–09/08

Table 50. CANGIT Register

CANGIT (S:9Bh)

CAN General Interrupt

Note:

1. This field is Read Only.

Reset Value = 0x00 0000b

7654

3210

CANIT

OVRTIM

OVRBUF

SERG

CERG

FERG

AERG

Bit

Number

Bit Mnemonic Description

7CANIT

General Interrupt Flag

(1)

This status bit is the image of all the CAN controller interrupts sent to the

interrupt controller.

It can be used in the case of the polling method.

Reserved

The values read from this bit is indeterminate. Do not set this bit.

5OVRTIM

Overrun CAN Timer

This status bit is set when the CAN timer switches 0xFFFF to 0x0000.

If the bit ETIM in the IE1 register is set, an interrupt is generated.

Clear this bit in order to reset the interrupt.

4OVRBUF

Overrun BUFFER

0 - no interrupt.

1 - IT turned on

This bit is set when the buffer is full.

Bit resetable by user.

see Figure 50.

3SERG

Stuff Error General

Detection of more than five consecutive bits with the same polarity.

This flag can generate an interrupt. resetable by user.

2CERG

CRC Error General

The receiver performs a CRC check on each destuffed received message

from the start of frame up to the data field.

If this checking does not match with the destuffed CRC field, a CRC error is

set.

This flag can generate an interrupt. resetable by user.

1FERG

Form Error General

The form error results from one or more violations of the fixed form in the

following bit fields:

CRC delimiter

acknowledgment delimiter

end_of_frame

This flag can generate an interrupt. resetable by user.

0AERG

Acknowledgment Error General

No detection of the dominant bit in the acknowledge slot.

This flag can generate an interrupt. resetable by user.

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